Frequency to digital conversion



June 24, 1958 J. v. BLANKENBAKER 2,840,709

FREQUENCY T0 DIGITAL CONVERSION 2 Sheets-Sheet 1 Filed July 2, 1956inkl/zx June 24, 1958- J. v. BLANKENBAKER 2,840,709

FREQUENCY Io DIGITAL CONVERSION 2 Sheets-Sheet 2 Filed July 2, 1956 N NW E United States Patent O Application This invention relates to asystem `for processing data and more particularly to a system forconverting alternating signals into pulses representing the frequency ofthe signals. The invention is especially adapted to be used withalternating signals having frequencies variable at any instant over aconsiderable range of values.

Considerable advances have been made in recent years in the lields ofdigital computers and data processing systems. For example, digitalcomputers have been built to solve a wide variety oi mathematicalproblems which have previously not been capable of mental solution orwhich have been solved only after much mental eort. Data processingsystems have been built to control inventories of large departmentstores and to control the operations of depositing and withdrawing moneyfrom banks. Data processing systems have also been built to control themovements of various machine tools such that the production of complexpieces can become largely automatic.

ln one type of apparatus for controlling the movements of a machinetool, notches are formed at spaced intervals in a member to indicateunitary movements of the member. For example, the movement of thecutting member on the machine tool past each notch represents anintegral unit of movement. A transducer such as a magnetic read head ismovable with the cutting member to produce signals representing theunits of movement. The notches may be provided with different magneticproperties than the raised portions between the notches so that themagnetic head can have signals induced in it in ac- `cordauce with themovements of the cutting member.

In order to provide a proper control over the movements of the cuttingmember, pulses must ybe produced to indicate the movements of thecutting head past the various notches. Since the movements of thecutting member may vary in rate over a considerable range of values, itIhas been difficult until now to produce output signals representingeach incremental unit of movement. This invention provides a system forproducing pulses representing each incremental unit of movement evenwith considerable variations in the rate at which the cutting member ismoving. The invention also has uses in any system in which the frequencyof an alternating signal having variable time characteristics must bemeasured.

ln the drawings:

Figure l is a circuit diagram somewhat in block form illustrating oneembodiment of the invention;

Figure 2 shows a plurality of curves which illustrate the outputvoltages `from certam of the members shown in Figure l; and

Figure 3 shows curves which illustrate on an amplified scale voltagewave forms produced at a particular terminal in Figure l.

ln the embodiment of the invention shown in Figure 1, a source 10 ofalternating signals is provided. The alternating signals may have aconstant frequency or may have a frequency variable at any instant overa considerable range of values. The alternating signals may be pro-2,840,709 Patented June 24, 1958.

ice

duced by a wide variety of means. For example, the alternating signalsmay be produced by a motor the speed of which can vary over asubstantial range. The alternating signals may also be induced in amagnetic head disposed in magnetic proximity to a notched track. Themagnetic head may be moved relative to the notched track in accordancewith the movements of a cutting member which is being automaticallydriven to produce components such as cams having complex shapes.

The alternating signals from the source 10 are introduced to the cathodeof a diode 12 having its plate connected to a source 14 of directvoltage so as to receive a negative voltage from the source. Thenegative voltage introduced to the plate of the diode 12 from the source14 may be in the order of -15 volts. The source 14 may be any suitablepower suply for providing a direct voltage. Preferably, the source 14may be constructed to provide voltages having stabilized amplitudes.

The alternating signals from the source 10 are also introduced to thecathode of a diode 16, the plate of which has common connections withtirst terminals of resistances 18, 20 and 22. The common connectionbetween the resistances 18, 20 and 22 and the plate of the diode 16 isindicate-d in Figure l as being made at a terminal 21. The secondterminal of the resistance 18 is connected to the source 14 to receive alsuitable positive voltage such as +109 volts from the source. Theresistance 18 may be provided with a suitable value such asapproximately 78,060 ohms. A connection is made from the second terminalof the resistance 20 to the plate of a diode 23 having its cathodeconnected to the left output terminal of a hip-flop 24. The diodes 16and 23 and the resistance 29 form a circuit commonly designated as anand circuit. This and network may be similar to other and networks shownin block form in Figure 1.

The liip-ilop 24 may be any suitable type of bistable member. known inthe art, the ip-lop 24 and other flip-flops in Figure l are shown inblock form. The ip-ilop 24 is provided with two input terminals and twooutput terminals. The input terminals of the ip-ilop 24 and of the otherflip-flops in Figure l will be respectively designated as the left andright input terminals and are shown as being positioned in the lowerleft and right portions of the block representing the flip-Hop. Theoutput terminals of the hip-flop 24 and of the other flip-hops in Figurel are respectively designated as the left and right output terminals andare shown as being positioned in the upper left and right positions ofthe block representing the ipflop. Special types of ip-ops such as thosedesignated as Manchester ilip-ops may also be used.

The left input terminal of the flip-flop 24 receives signals from an andnetwork 26, the operation of which is controlled by signals from theright output terminal of the flip-flop 24 and by clock signals from asource 30. The clock signals from the source 30 preferably occur atperiodic intervals and have a frequency greater than any of thefrequencies which may be provided for the alternating signals from thesource 10. For example, the clock signals from the source 30 may beobtained from a blocking oscillator or any other suitable type ofoscillator.

The clock signals may also be obtained from the clock channel of amagnetic drum such as has been normally included in various digitalcomputers and data processing systems.

The clock signals from the source 30 are introduced to one terminal ofan and network 32 as well as to one input terminal of the and etwork 26.The and network 32 also has signals applied to it from the left outputterminal of the flip-flop 24. The output terminal of the and network 32has a common connection with Since various types of bistable members arethe false state of operation.

, In addition to being connected to the resistances l,

and 22 and the plate of the diode 23, the terminal 2li is connected tothe left input terminal of a dip-dop 3e. The right input terminal of theilip-op 34 has signals applied to it from the right output terminal ofthe flip-liep 2e. The signals from the right output terminal of theiiip-liop 24 also pass to an input terminal of an and network 3i? havinganother input terminal connected to the left output terminal of theflip-liep 34. A connection is made from the output terminal of the andnetwork 36 to the left input terminal of the dip-dop 38. in like manner,the right input terminal of the flip-flop S is connected to the outputterminal ofV an and network 4d, the input terminals of whichV receivesignals from the right output terminals of the dip-flops 24- and 34.

Input terminals of an and network 42 are connected to the right outputterminals of the rlip-iiops 24 and 3S and the Vleft output terminal ofthe flip-op 34. Similarly, connections are made to input terminals of anand network 44 from the left output terminal of the iiip-iiop 33 and theright output terminalsof the dip-flops 24 and 34. The signals from theoutput terminals of the and networks 42 and 44 are respectivelyintroduced to the plates of diodes 46 and The cathodes of the diodes 46and 48 are connected to an output line Sti and to one terminal of aresistance 52, the other terminal of which is adapted to receive asuitable voltage such as approximately 100 volts from the source le. Theresistance 52 may be provided with a suitable value such asapproximately 55,000 ohms. The diodes 46 and 4S and the resistance 52form a circuit commonly designated as an or network.

at 6i? in Figure 2. Although the signals 6i) in Figure 7. are shown asbeing sinusoidal and at a constant frequency, the signals may have anywave shape and may be variable in frequency. During the negative swingof the alter nating signals o0, the amplitude of the signals may becomemore negative than a particular value represented by the voltageintroduced to the plate of the diode i?, from the source 14. When theamplitude of the signals 60 falls below the particular value, currentflows through a circuit including the source 14, the diode l2 and thesource 10. This causes the voltage at the cathode of the diode l2 tohave the same value as the potential introduced to the plate of thediode from the source 14. ln this way, the amplitude of the alternatingsignals from the source itl cannot decrease below a particular negativevalue. This is indicated at 62 in Figure 2.

As previously described, the clock signals trom the source 30 havea'frequency higher than the frequency oi the 'alternating signals fromthe source lil. The frequencies of the signals from the sources il) and3% may have an integral relationship or any other relationship whichwould not necessarily be an integral relationship. The clock signalsfrom the source 3d are introduced to the and networks 26 and 32. Theclock signals pass through the and network 26 when a relativelyV highvoltage is produced on the right output terminal of the ip-ilop 24.After passing through the and network 26, the clock signals areintroduced to the left input terminal of the flip-flop .24 to triggerthe ilip-ilop into the true state ofoperation. This is represented by arelatively high voltage'on the left output terminal of the ilip-ilop 24and a relatively low voltage on the right output terminal of theflip-flop. The relatively high voltages produced Y on the left outputterminal of the liip-op Zhi Aare indicated at 66 in Figure 2. n

Relatively high voltages are producedon the left output terminal of theflip-dop 24 in accordance with the logical equation:

r=TC (l) tra 4 where:

t-:the introduction of a triggering signal to the left input terminal ofthe flip-flop 24; :a relatively voltage the right output terminal of theflip-dop 25.1; and C=clock signals from the source 39.

The relatively high voltage on the left output terminal oi the flip-dop2d is introduced to the "anCV network 32 to prepare the and network forthe passage or clock signals from the source When the and network 32becomes prepared for operation, the next clock signal from the source3i) passes through the and network to the right input terminal of theflip-op 2d. This signal triggers the flip-dop Z4 to the false state ofoperation, as represented hy a relatively high voltage on the rightoutput terminal of the flip-dop 24 and a relatively low voltage on theleft output terminal of the ildp-liep. The

relatively low voltages'produeed on the left output ter.

minal ofY the dip-liep 24 are indicated at e?) in Figure 2. The flop-dop24 becomes triggered to its false state of operation in accordance withthe following logical'V equation:

Where YBecause of the relatively high voltage produced on the rightoutput terminal of the flip-liep 245, the and network 216 becomesprepared to pass the next clock signal The source Siti 1s adapted toprovide signals indicated from the source In this Way, the iiip-ilop 24becomes alternately triggered to its true and false states of operationupon the introduction of successive clock signals. This causes thevoltages 66 oi high amplitude and the voltages 68 of low amplitude to bealternately produced on the left output terminal of the flip-flop 24.The alternate signals of high and low amplitude on the left outputterminal of the liip-lop 24 have a frequency one half as great as thefrequency of the clock'signals from the source 3i?.

The signals produced on the left output terminal of the flip-Hop 24 areintroduced to the cathode of the diode 23. When the voltage 66 of highamplitude is produced on the left output terminal of the flip-flop 24,this voltage E prevents current from flowing through a circuit includingthe voltage source V14, the resistance i8, the resistance 2t?,

the diode 23 and the dip-d op 24 or at least minimizes any flow ofcurrent through this circuit. During the time that a relatively highvoltage is also introduced to the cathode of the diode 16 from thesource 1?, no current or at least a minimum current is able to flowthrough a circuit including the voltage source i4, the resistance 18,the diode i6 and the source lil. Because of this, a relatively highvoltage approaching the potential from the source i4 is produced at theterminal 21 upon the simultaneous introduction of high voltages to thecathodesrot the diodes 16 and 23.

A voltage approaching the potential of the source i4 is produced at theterminal 2l upon the simultaneous introduction of voltages of highamplitude to the cathodes of the diodes 16 and 23 even though theamplitude of the signals from the source l0 may rise above a particularvalue such as the potential from the source 14. This results from thefact'that current is not able to ow through the diode 16 when thepositive amplitude of the alternating signals 60 introduced to thecathode of the diode 16 is greater than the amplitude of the positivepotential introduced to the plate of the diode. The action of the diode16 in limiting the positive potential of the alternating signals isillustrated at 73 in Figure 2.

. Upon the occurrence of the next clock signal from the z source 30, arelatively low voltage is produced on the left output terminal of theilip-op 24 as previously described. This low voltage is introduced tothe cathode of the diode 23 to produce a liow of current throughacircuit including the source i4, the resistance 18, the resistance 20,the diode 23 and the dip-flop 24. Because of voltage produced across theresistance 18 by the flow of current through the resistance, a voltagedrop occurs at the terminal 21.

The drop in voltage at the terminal 21 is introduced to the left inputterminal of the flip-flop 34 to trigger the ip-op into the true state ofoperation, as represented by a relatively high voltage on the leftoutput terminal of the ip-op. The flip-dop 34 is triggered to its truestate of operation in accordance with the following logical equation:

r=FT (3) where:

:the introduction of a triggering signal to the left input terminal ofthe flip-dop 34;

F=the introduction of a signal of positive amplitude from the source 10,this signal being clamped as indicated at 73 in Figure 2; and

T=a signal of high amplitude from the left output terminal of theiiip-iiop 24.

In the next cycle of clock signals from the source 30, the lip-op 24becomes triggered to the false state of operation in accordance with thelogic expressed in Equation 2. This causes a relatively high voltage tobe introduced to the right input terminal of the flip-dop 34. At the endof this clock signal, the flip-liep 24 again becomes triggered to thetrue state such that the voltage on the right output terminal of theflip-dop changes from a high amplitude to a low amplitude.

The decrease in the amplitude of the voltage on the right outputterminal of the flip-dop 24 causes a triggering signal to be introducedto the right input terminal of the ip-op This signal triggers thedip-iop 34 tothe false state of operation, as represented by arelatively high voltage ori the right output terminal of the flip-dopand a relatively low voltage on the left output terminal of theHip-flop. The ip-op 34 becomes triggered to the false state of operationin accordance with the logical equation:

where li-.=the introduction of triggering signal to the right ini putterminal of the flip-iop 34; and

During the time that the alternating signals dil have a t positivepolarity and an amplitude above a particular value, the dip-dop 34becomes triggered to its true state in one clock cycle and triggered toits false state in the next clock cycle. This is in accordance with thelogic expressed in Equations 3 and 4. in this way, signals 70 of highamplitude and signals 72 of low amplitude are alternately produced onthe left output terminal of the flip-Hop E54. The signals "id and 72 andother signals produced by the flip-flop 34 may be considered as'rstcontrol signals. The alternate production of the signals 70 and 72continues until the amplitude of the alternating signals 60 decreasesbelow the particular positive value. The ip-cp 34 then remains in itsfalse state during the time that the negative halt cycles of thealternating signals 60 are being presented. This is indicated at 74 inFigure 2.

The positive voltage produced on the left output terminal of theflip-nop is introduced to the and network 36 to prepare the and networkfor operation, The and network 36 then passes a signal in the clockcycle in which a relatively high voltage simultaneously occurs Tfr- TRT(5) where m==the introduction of a triggering signal to the left inputterminal of the tlip-op 38; and

R=the production of a high voltage on the left output terminal of theflip-liep 34.

The voltages such as the voltage 76 produced on the output terminals ofthe dip-dop 33 may be Considered second control signals.

It has been explained previously that each of the flip- Hops 2.4, 34 and38 becomes triggered from one state of operation to the other at thetime that a negative signal is introduced to the dip-dop. Since theright input terminal of the flip-flop 3S is connected to the outputterminal of the and network` 40, the dip-dop 38 becomes triggered to itsfalse state when a negative signal passes through the and network 40.rThis should occur at the time that the voltage on the right outputterminal of the flip-flop 24 changes from a high amplitude to a lowamplitude. However, a signal can pass through the and network 40 fromthe dip-flop 24 only during the time that a relatively high voltage issimultaneously produced on the right output terminal of the tlip-op 34.

Since the production of a high voltage on the right output terminal ofthe ip-iop 34 is also controlled by the signals from the right outputterminal of the dip-lop 24, a signal is not able to pass through the andnetwork 40 unless the dip-flop 34 has been previously triggered to itsfalse state of operation. This cannot occur when the signals and 72 arebeing alternately produced in the flip-flop 34 during the occurrence ofsuccessive clock cycles. ln this way, the flip-liep 38 remains in itstrue state during the time that the signals 7='J` and "l2 arealternately produced on the lett output terminal of the ip-on 34. Inother words, the flip-flop cannet become triggered to its false stateunless the dip-flop 34 remains in its false state for at least twosuccessive clock cycles.

when the dip-dop 34 remains in its false state of operation for at leasttwo consecutive clock cycles, a relatively high voltage occurs on theright output terminal of the dip-d op 34 at the time that the voltage onthe right output terminal on the tiip-iiop 24 is changing from a highamplitude to a low amplitude. This causes a signal to pass .through theand network 4t) to the right input terminal of the flip-flop 38. Thesignal triggers the liipop 33 to the false state of operation, asrepresented by a relatively high voltage on the right output terminal ofthe Hip-flop and a relatively low voltage on the left output terminal ofthe dip-flop. The relatively low voltage on the left output terminal ofthe flip-flop is indicated at 78 in Figure 2. The ip-liop 38 becomestriggered to the false state of operation in accordance with the logicalequation:

where E :the introduction of a triggering signal to the right inputterminal of the dip-flop 33; and

itathe production of a high voltage on the right output terminal of thedip-flop 34.

T he and network 42 is able to pass a signal only when relatively highvoltages are simultaneously introduced to it from the left outputterminal of the Hip-flop 34 and the right output terminals of theip-tiops 24 and T18. As will be seen, this occursv only in the first ofseveral successive triggerings of the hip-flop 34 to the true state ofoperation during alternate clock cycles. This results from the fact thatthe dip-liep 38 is in the false state of operation only during the rsttime that the llipflop 34 is triggered to the true state and not duringthe successive times that the flip-flop 34 is triggered to the truestate.

Since the signals passing through the and networkY 42 have a highamplitude, current flows through a circuit including the ip-ops 24;, 34and 48, the and network 42, the diode 46, the resistance 52 and thevoltage source i4. This current produces a positive voltage across theresistance 52 and a rise in the voltage on the output line Sti. Theresultant pulse of voltage produced on the output line :itl is indicatedat 8@ in Figure 2. The pulses Si) are produced on the output line 50 inaccordance with the logical equation:

7 where z=an output signal on the line Si);

F=a relatively high voltage on the right output terminal of the dip-flop3S; and the other terms have previously been dened.

. Signals also pass through the and network 44 when relatively highvoltages are simultaneously produced on the left output terminal of theilip-iiop 38 and on the right output terminals of the dip-flops 24 and3d. This occurs only in the rst cycle in which the iiip-op 70 is nottriggered to its true state after it has been previously triggered tothe false state. The signals are able to pass through the and network 44only at such times since these are the only times that a relatively highvoltage still remains on the left output terminal of the ipop 3s.

The signals passing through the and network 44 produce a tiow of currentthrough the diode 48 and the resistance 52 such that pulses of positiveamplitude are produced on the output line 50. The pulses of positiveamplitude produced on the output line 50 by the passage of signalsthrough the and network #i4 are indicated at 82 in Figure 2. The pulses32 are produced on the output line 5t) in accordance with the logicalequation:

where ,i

M :a relativelyV high voltage on the left output terminal of thelip-ilop 33; and the other terms have previously been defined.

lt will be noticed that each of the pulses 89 and 82 has a durationcorresponding to the duration of one of the clock signals from thesource 30. The pulses 3i) are produced during the positive half cyclesof the alternating signals ed. Similarly, the pulses S2 are produced inthe negative half cycles of the alternating signals 6? or at least at atime approaching the beginning of the negative half cycles in thealternating signals 60. By introducing the pulses 80 and 82 to separateoutput terminals, a distinction can be obtained between the positive andnegative half cycles of the alternating signals. lf it should be desiredonly to indicate the occurrence of successive cycles of the alternatingsignals dii, both of the pulses 8d and 82 can be included as onealternative. This alternative is shown in Figure l and is illustrated inFigure 2. As another alternative, either the pulses Si) or the pulses 92can be used to indicate the occurrence of successive cycles in thealternating signals 60.

At some time during the rise in amplitude of the alternating signals tl,the flip-flop 34 is first triggered to the true state of operation inaccordance with the logic eX- pressed in Equation 3. After two morecycles of clock 22 to the terminal 2l.

Vthe terminal from the source ld.

signals, the hip-flopv 3S becomes triggered to its true stateof'operation in accordance with the logic expressed in Equation 5. Thismay also be seen from the curves shown in Figure 2. Y

When the flip-*iop 38 becomes triggered to the true state of operation,a relatively high voltage is introduced from the left output terminal ofthe hip-flop 33 through the resistance 22 to the terminal 2l. The outputvoltage fed back from the tiip-op 3S to the terminal 2l helps inmaintaining the terminal at a high amplitude. l'n this way, a negativetriggering signal having a large amplitude is produced at the terminal21 when the voltage on the left output terminal of the flip-flop 24changes from a high amplitude to a low amplitude. This may be s' acomparison in the amplitudes of two successive trig ering signals 845and S8 produced at the terminal 2i., The signal Se is produced duringthe time that the iip-ilop 38 is still in its false state of operationand the ynal 88 is produced during the time that the hip-liep 33 Vis inits true state of operation. The signal SS has a greater amplitude thanthe signal S6 since it starts from a higher positive amplitude than thesignal 86.

In this way, the flip-flop 38 operates to facilitate the triggering ofthe hip-flop 34 to the truerstate of operation upon the occurrence ofalternate clock signals during the time that the alternating signals 6dhave a positive amplitude above a particular valuel As previouslydescribed in connection with the logic expressed in Equations 7 and 8,this is important in insuring that only the output pulses 80 areproduced during the positive half cycles of the alternating signals.

it has been previously described that the flip-liep 33 is triggered toits false state of operation when the amplitude of the alternatingsignals e@ falls below a particular positive value. The triggering ofthe flip-flop 38 to its false state or" operation is indicated at 7d inFigure 2. When the hip-flop 3S is triggered to its false state ofoperation, a relatively low voltage is introduced from the left-outputterminal of the flip-dop through the resistance This low voltage causesthe magnitude of the positive voltage at the terminal 'Ztl to decreaseeven though a constant voltage is introduced to Because of the decreasein the magnitude of the voltage at the terminal 2l,

" a decrease is obtained in the amplitude of the negative duced duringthe time that the dip-dop 3% is in its true state and the signals 92 areproduced during the time that the flip-flop Sil is in its false state.By decreasing the amplitude of the signals in the terminal 2l from thatillustrated by the signals 9i? to that illustrated by the signals 92,the amplitude oi the negative signals become too low to trigger theflip-flop 3d to the true state of operation. This is desirable since thedip-flop should remain in its false state of operation during the timethat the amplitude of the alternating signals are below the particularpositive value. This is indicated at 74 in Figure 2.

lt should be appreciated that the alternating signals 6i? may beproduced by physical movements of a transducer. For example, a cuttingmember and a transducer such as a magnetic read head may be included indata processing apparatus for automatically' controlling the movementsof the cutting rncmher to produce components such as cams having complexshapes. The magnetic read head may be moved in synchronization with thecutting member past a track having notches and raised portionsalternatelyV disposed relative to one another.

Upon the movements of the magnetic read head past the notches and raisedportions, signals corresponding to the alternating signals d@ areinduced in the head. These signals have at any instant a frequencydependent upon the rate movement the magnetic head past the notches andraised portions. One type of magnetic read head capable of being used insuch apparatus is disclosed in detail and claimed in co-pendingapplication Serial No. 588,7ll filed lune l, 1956 by David F. Brower,and assigned to the same assignee as this application.

lt will be seen from the above discussion that the system constitutingthis invention can be used in any apparatus where the frequency ofalternating signals must be measured. The system is es ecially ladaptedbe use in apparatus where the frequency of the alternating signals mayvary over considerable ranges and where the frequency of the alternatingsignals rnay fall to relatively low values.

l claim:

l. Apparatus for converting alternating signals into pulses indicatingthe frequency of the signals, including, means for providing clocksignals having a frequency higher than the frequency of the alternatingsignals, means for sampling the amplitude of the alternating signals atperiodic intervals rela ed to the frequency of the clock signals toproduce first control signals at a frequency dependent upon thefrequency of the clock signals during at least a first polarity in thealternating signals, means for sampling the rst control signals inaccordance with the frequency of the clock signals to produce secondcontrol signals having an amplitude dependent upon the regularity offirst control signals, and means for operating upon the first and secondcontrol signals and the clock signals in a particular manner to obtainoutput pulses at a frequency related to the frequency of the alternatingsignals.

2. Apparatus for converting alternating signals intoV pulses indicatingthe frequency of the signals, including, means for providing clocksignals having a frequency higher than the frequency of the alternatingsignals, means including a first bistable member operative upon thealternoting signals and the clock signals for providing first controlsignals having changes in characteristics at a frequency related to thefrequency of the clock signals during at least one polarity of thealternating signals, means including a second bistable member operativeupon the first ycontrol signals and the clock signals for providingsecond control signals having an amplitude continued until theinterruption in the regularity of the rst control signals, and meansincluding at least one and network for operating upon the first andsecond control signals and the clock signals to produce pulses having afrequency reprepresenting the frequency of the alternating signals.

3. Apparatus for converting alternating signals into pulses indicatingthe frequency of the signals, including, means for providing clocksignals at a frequency higher than the frequency of the alternatingsignals, a first bistable member having first and second states ofoperation, means including the first bistable member for triggering themember to the rst and second states of operation at a rate dependentupon the frequency of the clock signals during at least a portion ofeach alternating signal, a second bistable member having first andsecond states of operation, means for combining the signals from theclock signal means and the first bistable member to trigger the secondbistable member in accordance with the operation of' the first bistablemember and after a delay dependent upon the regularity in the triggeringof the first bistable member to the first and second states ofoperation, and means for combining the signals from the clock signalmeans and from the first and second bistable members to produce outputpulses having a rate indicating the frequency of the alternatingsignals.

4. Apparatus for converting alternating signals into pulses indicatingthe frequency of the signals, including, means for providing clocksignals at a frequency higher than the frequency of the alternatingsignals, first electrical circuitry for providing first and secondcontrol signals representing the opposite polarities of the alternatl0ing signals and for presenting the signals on an alternate basis at arate related to the frequency of the clock signals during at least aportion of each cycle of alternating voltage, second electricalcircuitry responsive to the signals from the clock means and from thefirst electrical circuitry for providing third and fourth controlsignals having rise times delayed from particular ones of the first andsecond control signals by times related to the frequency of the clocksignals and having durations dependent upon the periodicity of the firstand second control signals, and electrical circuitry responsive to thesignals from the clock means and from the first and second electricalcircuitry for producing output pulses having a frequency correspondingto the frequency of `the alternating signals.

5. Apparatus for converting alternating signals into pulses indicatingthe frequency of the signals, including, means for providing clocksignals at a frequency higher than the frequency of the alternatingsignals, means for operating on the alternating signals and the clocksignals to provide first control signals having amplitudes alternatingbetween rst and second levels during a first polarity in the alternatingsignals and having the second level during the opposite polarity in thealternating signals, means for operating on the first control signalsand the clock signals to produce second control signals having a firstamplitude during the alternation of the first control signals betweenthe first and second amplitudes and having a second amplitude during theproduction of the second level in the first control signals, and meansfor combining the first and second control signals and the clock signalsto produce output pulses at a rate corresponding to the frequency of thealternating signals.

6. Apparatus for converting alternating signals into pulses indicatingthe frequency of the signals, including, means for providing clocksignals at a frequency higher than the frequency of the alternatingsignals, means including at least a first and network for operating uponthe alternating signals and the clock signals to produce first controlsignals having amplitudes alternating between first and second levels insuccessive clock cycles during particular characteristics in thealternating signals and having the second characteristics at the othertimes in the alternating signals and during the occurrence of successiveclock signals, means including at least a second and network foroperating upon the first control signals and the clock signals toproduce second control signals having a first amplitude upon thealternation in the amplitude of the first control signals and having asecond amplitude upon the occurrence of the first control signals havingthe second characteristics in the successive clock cycles, and meansincluding at least a third and network for operating upon the first andsecond control signals and the clock signals to produce pulses having arate representing the frequency of the alternating signals.

7. Apparatus for converting alternating signals into pulses indicatingthe frequency of the signals, including, means for providing clocksignals at a frequency higher than the frequency of the alternatingsignals, means including at least a first and network and a firstbistable member for operating upon the alternating signals and the clocksignals to produce in the bistable member' control signals having firstand second amplitudes during successive clock signals upon theoccurrence in the ternating signals of amplitudes differing in a firstrespect from a particular value and having the second amplitude duringsuccessive clock cycles up'on the occurrence in the alternating signalsof amplitudes differing in a second respect opposite to the firstrespect from the particular value, means including at least a second andnetwork and a second bistable member for operating upon the firstcontrol signals and the clock signals to produce in the bistable membersecond control signals having a first amplitude a particular number ofclock cycles after the initiation in the production of the alternatingcharacteristics in the amplitudes of the first control signals andhaving a second amplitude a particular number of clock cycles after theinitiation in'the production of the second amplitude in the firstcontrol signals during successive clock cycles, and means including atleast a third and network for operating upon the first and secondcontrol signals and the clock signals to produce output pulses having aate corresponding to the frequency of the alternating signals.

8. Apparatus for converting alternating signals into pulses indicatingthe frequency of the signals, including, means for providing clocksignals at a frequency higher than the frequency of the alternatingsignals, a first bistable member having first and second states ofoperation, means including at least a Vrst and network for co ibiningthe alternating signals and first alternate clocl; signals to triggerthe first bistable member into the first state of operation in the firstalternate clock cycles during the occurrence of first characteristics inthe alternating signals, means for introducing second alternate clocl.signals to the first bistable member to trigger the first bistablemember into the second state of operation in the second alternate clockcycles during the occurrence of the first characteristics in thealternating signals and to maintain the bistable member in the secondstate of operation at the other times in the alternating signals, asecond bistable member having first and second states of operation,means including at least a second and network for combining the signalsfrom the first bistable member and the second alternate clock signals totrigger the second bistable member to the first state of operation uponthe simultaneous occurrence of the first state of operation in the rstbistable member and the second alternate clock signals and to maintainthe second bistable member in the first state of operation during thealternation of the first bistable member between the first and. secondstates of operation in alternate clock cycles, means including at leasta third an networl; for combining the signals from the first bistablemember and the second alternate clock signals to trigger the secondbistable member to the second state of operation upon the simultaneousoccurrence of the second state of operation in the first bistable memberand the second alternate clock signals, and means including at least afourth and network for combining the signals from the first and secondbistable members and the clock signals to produce output pulses having afrequency corresponding to the frequency of the alternating signals andhaving a duration corresponding to the frequency of the clock signals.

9. Apparatus for converting alternating signals into pulses indicatingthe frequency of the signals, including, means for providing lclocksignals having a frequency higher than the frequency of the alternatingsignals, means for sampling the amplitude of the alternating signals atperiodic intervals related to the frequency of the clock signals toproduce rst control signals having characteristics alternating at afrequency dependent upon the frequency of the clock signals and forproducing the alternating characteristics in the first control signalsduring at least a first polarity in the alternating signals, means forsampling the first control signals in accordance with the frequency ofthe clock signals to produce second control signals having firstcharacteristics during the production of the alternating characteristicsin theV first control signals and having second characteristics at theother times in the alternating signals, meansV for providing for afeedback of the second control signals to the first control means tofacilitate the production of the alternating characteristics in thefirst control signals during the first polarity in the alternatingsignals and to retard the production of the alternating characteristicsin the firstcontrol signals during a second polarity in the alternatingsignals, and means for operating upon the first and second controlsignals and the output signals in a particular relationship to obtainoutput pulses at a frequency related to the frequency of the alternatingsignals. l0. Apparatus for convertiniy alternating signals into pulsesindicating the frequency of the signals, including, means for providingclock. signals at a frequency higher than the frequency of thealternating signals, including at least a first and network a firstbistable member for operating on the alternating signals and the clocksignals to provide first control signals having amplitudes altern tingbetween first and second levels during the occorre, c of firstcharacteristics in the alternating signals and having the second level famplitude during the occurrence of second characteristics in thealternating signals, means including at least a second and network and asecond bistable mem-ber for operating on the nrst control signals andthe clock signals to provide second control signals having a rstamplitude during the alternation of the rst control signals between thefirst and second amplitudes and having a second amplitude during theproduction of the second level of amplitude in the first control signalsduring successive half cycles, means for providing a feedback betweenthe second bistable member and the first and network to facilitate theproduction of the alternations in the first control signals during thefirst characteristics in the alternating signals and to retard theproduction of the alternations in the first control signals during t Aesecond characteristics in the alternating signals, and means forcombining the first and second control signals and the clock signals toproduce output pulses at a rate representing the frequency of thealternating signals.

11. Apparatus for converting alternating signals into pulses indicatingthe frequency and the polarity of the signals, including, means forproviding clocl; signals at Va frequency higher than the frequency ofthe alternating signals, first means for operating upon the alternatingsignals and the clock signals to produce first control signals havingalternating characteristics during the occurrence of firstcharacteristics in the alternating signals and having stablecharacteristics during the occurrence in the alternating signals ofsecond characteristics different from the first characteristics, secondmeans for operating upon the first control signals and the clock signalsto produce second control signals having first characteristics upon theoccurrence of the alternatingcharacteristics in the first controlsignals and having secon-:l characteristics upon the occurrence of thestable characteristics in the first control signals, first output fneansfor operating upon the first and second control Qials and the clocksignals in a first particular relationship to produce first outputsignals which have a rate respreseuting the frequency of the alternatingsignals and which occur upon a change in the alternating signals to thefirst characteristics, and second output means for operating upon thefirst and second control signals and the clock si nais in a secondparticular relationship to pr duce se 1" output signals which have arate represe ng the quency of the alternating signals and which occur ua change in the alternating signals to second teristcs.

l2. Apparatus for converting alternating signals into pulses indicatingthe frequency and pol t* J signals, including, means for providing clocksignals having a frequency higher than 'the frequencf of thealternating'signals, means including at least one and network forsampling the amplitude of the alternating signals at periodic intervalsrelated to the frequency of the clock signals to produce first controlsignals having alternating characteristics at a frequency related to thefrequency of the clock signals during the occurrence of firstcharacteristics in the alternating signals, means cluding at least oneand network first control signals in accordance with the frequency ofthe clock signals to produce second control signals having firstcharacteristics upon the occurrence of alternating characteristics inthe first control signals and having second -characteristics upon theoccurrence in the a1- ternating signals of second characteristicsdifferent from the first characteristics, means including an and networkfor operating upon the first and second control signals yand the clocksignals in a first particular relationship to produce first outputsignals at a rate corresponding to the frequency of the alternatingsignals and representing the first characteristics in the alternatingsignals, 'and means including an and network for operating upon the rst`and second control signals and the clock signals in a second particularrelationship to produce second output signals at a rate corresponding tothe frequency of the alternating signals and representing the secondcharactertistics in the alternating signals.

13. Apparatus for converting alternating signals into pulses indicatingthe frequency and the polarity of the signals, including, means forproviding clock signals having a frequency higher than the frequency ofthe alternating signals, electrical circuitry for sampling the amplitudeof the alternating signals at periodic intervals related to thefrequency of the clock signals to produce first control signals havingcharacteristics alternating at a frequency dependent upon the frequencyof the clock signals during at least a first polarity of the alternatingsignals and having stable characteristics during the remaining portionof the alternating signals, electrical circuitry operative upon thefirst control signals and the clock signals for providing second controlsignals having first or second characteristics dependent upon theproduction of alternating or stable characteristics in the first controlsignals, electrical `circuitry operative upon the first and secondcontrol signals and the clock signals in a first relationship to producefirst output signals in successive cycles of the alternating vsignalsand during the first polarity of the alternating signals to representthe frequency and polarity of the alternating signals, `and electricalcircuitry operative upon the first and second control signals and theclock signals in a second relationship to produce second output signalsin successive cycles of the lalternating signals and during the secondpolarity of the alternating signals to represent the frequency `andpolarity of the alternating signals.

l4. Apparatus as :set forth in claim 7, including, means for providing afeedback from the second bistable member to the first and network forfacilitating the production of the alternations in the amplitudes of thefirst control signals during the occurrence in the alternating signalsof amplitudes differing in the first respect from the particular valueand for facilitating the maintenance of the second amplitude in thefirst control signals during the `occurrence in the alternating signalsof amplitudes differing in the second respect from the particular value,the third and network being connected to produce output pulses only upona first polarity in the alternating signals, and means including afourth and network for operating upon the first and second controlsignals and the clock signals to produce output pulses having a ratecorresponding to the frequency of the alternating signals and only upona second polarity in the alternating signals.

References Cited in the file of this patent UNITED STATES PATENTS2,743,419 Chatterton et al. Apr. 24, 1956 2,769,595 Bagley Nov. 6, 1956

